Resolving global coupling timing and slew violations for buffer-dominated designs

A mechanism is provided for resolving uplift or coupling timing problems and slew violations without sacrificing late mode timing in integrated circuit (IC) designs. Responsive to a request being received to generate a new IC design, for each net in a plurality of nets in the new IC design, a determination is made as to whether the net is routable through a cell in a plurality of cells using a cost function associated with the cell such that a coupling capacitance associated with the net is equal to or below a predetermined coupling capacitance threshold. Responsive to net being able to be routed through the cell with the coupling capacitance being equal to or below the threshold, the net is assigned to at least one track within the cell. Responsive to all nets in the new IC design being routed, a new IC design is generated.