SRAM bitcell data retention control for leakage optimization

An integrated circuit includes a static random access memory (SRAM) array coupled to a first voltage supply node and a second voltage supply node. The first and second voltage supply nodes provide a retention voltage across the SRAM array. A current limiter is disposed between the SRAM array and the...

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Bibliographische Detailangaben

Hauptverfasser:	HSU KUOYUAN, TANG YUKIT
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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