Flexible pin allocation
A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins o...
Gespeichert in:
Hauptverfasser: | , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | VADUVATHA SRINIVAS SEN DIBYENDU GUPTA ANURAG P VENKATARAMAN SRINIVAS GARAPALLY PRAVEEN BRISTOL NORMAN |
description | A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins of the memory. The controller is also configured to redirect the input signals, within the controller, based on the allocation of the pads and output the input signals from the controller into the pads. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8341584B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8341584B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8341584B13</originalsourceid><addsrcrecordid>eNrjZBB3y0mtyEzKSVUoyMxTSMzJyU9OLMnMz-NhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwRbGJoamFiZOhsZEKAEAifQhqA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Flexible pin allocation</title><source>esp@cenet</source><creator>VADUVATHA SRINIVAS ; SEN DIBYENDU ; GUPTA ANURAG P ; VENKATARAMAN SRINIVAS ; GARAPALLY PRAVEEN ; BRISTOL NORMAN</creator><creatorcontrib>VADUVATHA SRINIVAS ; SEN DIBYENDU ; GUPTA ANURAG P ; VENKATARAMAN SRINIVAS ; GARAPALLY PRAVEEN ; BRISTOL NORMAN</creatorcontrib><description>A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins of the memory. The controller is also configured to redirect the input signals, within the controller, based on the allocation of the pads and output the input signals from the controller into the pads.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20121225&DB=EPODOC&CC=US&NR=8341584B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20121225&DB=EPODOC&CC=US&NR=8341584B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>VADUVATHA SRINIVAS</creatorcontrib><creatorcontrib>SEN DIBYENDU</creatorcontrib><creatorcontrib>GUPTA ANURAG P</creatorcontrib><creatorcontrib>VENKATARAMAN SRINIVAS</creatorcontrib><creatorcontrib>GARAPALLY PRAVEEN</creatorcontrib><creatorcontrib>BRISTOL NORMAN</creatorcontrib><title>Flexible pin allocation</title><description>A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins of the memory. The controller is also configured to redirect the input signals, within the controller, based on the allocation of the pads and output the input signals from the controller into the pads.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBB3y0mtyEzKSVUoyMxTSMzJyU9OLMnMz-NhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwRbGJoamFiZOhsZEKAEAifQhqA</recordid><startdate>20121225</startdate><enddate>20121225</enddate><creator>VADUVATHA SRINIVAS</creator><creator>SEN DIBYENDU</creator><creator>GUPTA ANURAG P</creator><creator>VENKATARAMAN SRINIVAS</creator><creator>GARAPALLY PRAVEEN</creator><creator>BRISTOL NORMAN</creator><scope>EVB</scope></search><sort><creationdate>20121225</creationdate><title>Flexible pin allocation</title><author>VADUVATHA SRINIVAS ; SEN DIBYENDU ; GUPTA ANURAG P ; VENKATARAMAN SRINIVAS ; GARAPALLY PRAVEEN ; BRISTOL NORMAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8341584B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>VADUVATHA SRINIVAS</creatorcontrib><creatorcontrib>SEN DIBYENDU</creatorcontrib><creatorcontrib>GUPTA ANURAG P</creatorcontrib><creatorcontrib>VENKATARAMAN SRINIVAS</creatorcontrib><creatorcontrib>GARAPALLY PRAVEEN</creatorcontrib><creatorcontrib>BRISTOL NORMAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>VADUVATHA SRINIVAS</au><au>SEN DIBYENDU</au><au>GUPTA ANURAG P</au><au>VENKATARAMAN SRINIVAS</au><au>GARAPALLY PRAVEEN</au><au>BRISTOL NORMAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Flexible pin allocation</title><date>2012-12-25</date><risdate>2012</risdate><abstract>A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins of the memory. The controller is also configured to redirect the input signals, within the controller, based on the allocation of the pads and output the input signals from the controller into the pads.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US8341584B1 |
source | esp@cenet |
subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Flexible pin allocation |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T06%3A11%3A30IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=VADUVATHA%20SRINIVAS&rft.date=2012-12-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8341584B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |