Memory leakage and data retention control

A circuit with leakage and data retention control includes at least one memory cell in a first memory array. The at least one memory cell is coupled to a first power supply voltage and a virtual ground. The circuit includes a current source and an NMOS transistor. The drain of the NMOS transistor is...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	CHANG JACKLYN, HSU KUOYUAN (PETER), TANG YUKIT
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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