Semiconductor package
A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and ha...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | SU YUANANG HUANG SHIH-FU CHEN KUANG-HSIUNG HSIEH PAO-MING APPELT BERND KARL |
| description | A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8330267B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8330267B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8330267B23</originalsourceid><addsrcrecordid>eNrjZBANTs3NTM7PSylNLskvUihITM5OTE_lYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxUBVqXmpJfGhwRbGxgZGZuZORsZEKAEATNIhEw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor package</title><source>esp@cenet</source><creator>SU YUANANG ; HUANG SHIH-FU ; CHEN KUANG-HSIUNG ; HSIEH PAO-MING ; APPELT BERND KARL</creator><creatorcontrib>SU YUANANG ; HUANG SHIH-FU ; CHEN KUANG-HSIUNG ; HSIEH PAO-MING ; APPELT BERND KARL</creatorcontrib><description>A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20121211&DB=EPODOC&CC=US&NR=8330267B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20121211&DB=EPODOC&CC=US&NR=8330267B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SU YUANANG</creatorcontrib><creatorcontrib>HUANG SHIH-FU</creatorcontrib><creatorcontrib>CHEN KUANG-HSIUNG</creatorcontrib><creatorcontrib>HSIEH PAO-MING</creatorcontrib><creatorcontrib>APPELT BERND KARL</creatorcontrib><title>Semiconductor package</title><description>A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBANTs3NTM7PSylNLskvUihITM5OTE_lYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxUBVqXmpJfGhwRbGxgZGZuZORsZEKAEATNIhEw</recordid><startdate>20121211</startdate><enddate>20121211</enddate><creator>SU YUANANG</creator><creator>HUANG SHIH-FU</creator><creator>CHEN KUANG-HSIUNG</creator><creator>HSIEH PAO-MING</creator><creator>APPELT BERND KARL</creator><scope>EVB</scope></search><sort><creationdate>20121211</creationdate><title>Semiconductor package</title><author>SU YUANANG ; HUANG SHIH-FU ; CHEN KUANG-HSIUNG ; HSIEH PAO-MING ; APPELT BERND KARL</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8330267B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SU YUANANG</creatorcontrib><creatorcontrib>HUANG SHIH-FU</creatorcontrib><creatorcontrib>CHEN KUANG-HSIUNG</creatorcontrib><creatorcontrib>HSIEH PAO-MING</creatorcontrib><creatorcontrib>APPELT BERND KARL</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SU YUANANG</au><au>HUANG SHIH-FU</au><au>CHEN KUANG-HSIUNG</au><au>HSIEH PAO-MING</au><au>APPELT BERND KARL</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor package</title><date>2012-12-11</date><risdate>2012</risdate><abstract>A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US8330267B2 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Semiconductor package |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-10T09%3A12%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SU%20YUANANG&rft.date=2012-12-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8330267B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |