Cached memory system and cache controller for embedded digital signal processor

A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SIH GILBERT CHRISTOPHER, WEI JIAN, HSU DE D, HIGGINS RICHARD, SAKAMAKI CHARLES E
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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