Method and system to optimize semiconductor products for power, performance, noise, and cost through use of variable power supply voltage compression

A method of integrated circuit design and, more particularly, a method and system to optimize semiconductor products for power, performance, noise, die area, and cost through use of variable power supply voltage compression. The method is implemented in a computer-based tool and includes: embedding relationships in an optimization tool running on a computing device, wherein the relationships are based at least partly on performance, power-supply noise, die area, and power; inputting a set of product data and a set of technology data in the optimization tool running on the computing device; and determining product design parameters including power supply voltage, switching-noise-induced power supply voltage variation, and decap area. The determining is based on the relationships, the product data, and the technology data and is performed using the computing device running the optimization tool.