Trench decoupling capacitor formed by RIE lag of through silicon via (TSV) etch

Trench decoupling capacitor formed by RIE lag of through silicon via (TSV) etch

A trench decoupling capacitor is formed using RIE lag of a through silicon via (TSV) etch. A method includes etching a via trench and a capacitor trench in a wafer in a single RIE process. The via trench has a first depth and the capacitor trench has a second depth less than the first depth due to R...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: BERNSTEIN KERRY, WHITE FRANCIS ROGER
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A trench decoupling capacitor is formed using RIE lag of a through silicon via (TSV) etch. A method includes etching a via trench and a capacitor trench in a wafer in a single RIE process. The via trench has a first depth and the capacitor trench has a second depth less than the first depth due to RIE lag.