Semiconductor device having resistance based memory array and method of operation associated therewith

In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	WANG QI, CHO WOOYEONG, CHOI HYUNHO, LEE KWANGJIN, KIM KWANGHO, KIM TAEK-SUNG, KIM HYE-JIN, LEE YONG-JUN
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
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