Reference signal synchronized to clock signal

A system comprising a clock board comprising a clock generator, a first board comprising an indicator and coupled to said clock board. The clock generator generates a clock signal, and the first board is configured to receive said clock signal. The first board further comprises a clock synchronizing...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: MACIOROWSKI DAVID
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator MACIOROWSKI DAVID
description A system comprising a clock board comprising a clock generator, a first board comprising an indicator and coupled to said clock board. The clock generator generates a clock signal, and the first board is configured to receive said clock signal. The first board further comprises a clock synchronizing unit that synchronizes a reference signal with said clock signal and generates a blink cadence signal based on said reference signal. The blink cadence signal is configured to drive the indicator of said first board. A failure by said first board to receive said clock signal causes the clock synchronizing unit of said first board to maintain the reference signal and generate said blink cadence signal based on said reference signal.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8237579B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8237579B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8237579B23</originalsourceid><addsrcrecordid>eNrjZNANSk1LLUrNS05VKM5Mz0vMUSiuzEvOKMrPy6xKTVEoyVdIzslPzoZK8jCwpiXmFKfyQmluBgU31xBnD93Ugvz41OKCxOTUvNSS-NBgCyNjc1NzSycjYyKUAACQMSoy</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Reference signal synchronized to clock signal</title><source>esp@cenet</source><creator>MACIOROWSKI DAVID</creator><creatorcontrib>MACIOROWSKI DAVID</creatorcontrib><description>A system comprising a clock board comprising a clock generator, a first board comprising an indicator and coupled to said clock board. The clock generator generates a clock signal, and the first board is configured to receive said clock signal. The first board further comprises a clock synchronizing unit that synchronizes a reference signal with said clock signal and generates a blink cadence signal based on said reference signal. The blink cadence signal is configured to drive the indicator of said first board. A failure by said first board to receive said clock signal causes the clock synchronizing unit of said first board to maintain the reference signal and generate said blink cadence signal based on said reference signal.</description><language>eng</language><subject>ALARM SYSTEMS ; ORDER TELEGRAPHS ; PHYSICS ; SIGNALLING ; SIGNALLING OR CALLING SYSTEMS</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120807&amp;DB=EPODOC&amp;CC=US&amp;NR=8237579B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120807&amp;DB=EPODOC&amp;CC=US&amp;NR=8237579B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MACIOROWSKI DAVID</creatorcontrib><title>Reference signal synchronized to clock signal</title><description>A system comprising a clock board comprising a clock generator, a first board comprising an indicator and coupled to said clock board. The clock generator generates a clock signal, and the first board is configured to receive said clock signal. The first board further comprises a clock synchronizing unit that synchronizes a reference signal with said clock signal and generates a blink cadence signal based on said reference signal. The blink cadence signal is configured to drive the indicator of said first board. A failure by said first board to receive said clock signal causes the clock synchronizing unit of said first board to maintain the reference signal and generate said blink cadence signal based on said reference signal.</description><subject>ALARM SYSTEMS</subject><subject>ORDER TELEGRAPHS</subject><subject>PHYSICS</subject><subject>SIGNALLING</subject><subject>SIGNALLING OR CALLING SYSTEMS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNANSk1LLUrNS05VKM5Mz0vMUSiuzEvOKMrPy6xKTVEoyVdIzslPzoZK8jCwpiXmFKfyQmluBgU31xBnD93Ugvz41OKCxOTUvNSS-NBgCyNjc1NzSycjYyKUAACQMSoy</recordid><startdate>20120807</startdate><enddate>20120807</enddate><creator>MACIOROWSKI DAVID</creator><scope>EVB</scope></search><sort><creationdate>20120807</creationdate><title>Reference signal synchronized to clock signal</title><author>MACIOROWSKI DAVID</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8237579B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>ALARM SYSTEMS</topic><topic>ORDER TELEGRAPHS</topic><topic>PHYSICS</topic><topic>SIGNALLING</topic><topic>SIGNALLING OR CALLING SYSTEMS</topic><toplevel>online_resources</toplevel><creatorcontrib>MACIOROWSKI DAVID</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MACIOROWSKI DAVID</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Reference signal synchronized to clock signal</title><date>2012-08-07</date><risdate>2012</risdate><abstract>A system comprising a clock board comprising a clock generator, a first board comprising an indicator and coupled to said clock board. The clock generator generates a clock signal, and the first board is configured to receive said clock signal. The first board further comprises a clock synchronizing unit that synchronizes a reference signal with said clock signal and generates a blink cadence signal based on said reference signal. The blink cadence signal is configured to drive the indicator of said first board. A failure by said first board to receive said clock signal causes the clock synchronizing unit of said first board to maintain the reference signal and generate said blink cadence signal based on said reference signal.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US8237579B2
source esp@cenet
subjects ALARM SYSTEMS
ORDER TELEGRAPHS
PHYSICS
SIGNALLING
SIGNALLING OR CALLING SYSTEMS
title Reference signal synchronized to clock signal
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-15T00%3A25%3A36IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MACIOROWSKI%20DAVID&rft.date=2012-08-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8237579B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true