Mitigating context switch cache miss penalty

Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably c...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	DELANO ERIC R, CALLISTER JAMES R, BHATIA ROHIT, WALKER SHAWN KENNETH, GIBSON MARK M
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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