Power semiconductor device having low gate input resistance

A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal laye...

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Hauptverfasser: LIAO SHIAN-HAU, LIN JIA-FU, LIN WEIIEH, YANG GUO-LIANG
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Sprache:eng
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creator LIAO SHIAN-HAU
LIN JIA-FU
LIN WEIIEH
YANG GUO-LIANG
description A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8178923B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8178923B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8178923B23</originalsourceid><addsrcrecordid>eNrjZLAOyC9PLVIoTs3NTM7PSylNLskvUkhJLctMTlXISCzLzEtXyMkvV0hPLElVyMwrKC1RKEotziwuScxLTuVhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwRaG5haWRsZORsZEKAEAiiwvrQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Power semiconductor device having low gate input resistance</title><source>esp@cenet</source><creator>LIAO SHIAN-HAU ; LIN JIA-FU ; LIN WEIIEH ; YANG GUO-LIANG</creator><creatorcontrib>LIAO SHIAN-HAU ; LIN JIA-FU ; LIN WEIIEH ; YANG GUO-LIANG</creatorcontrib><description>A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120515&amp;DB=EPODOC&amp;CC=US&amp;NR=8178923B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120515&amp;DB=EPODOC&amp;CC=US&amp;NR=8178923B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LIAO SHIAN-HAU</creatorcontrib><creatorcontrib>LIN JIA-FU</creatorcontrib><creatorcontrib>LIN WEIIEH</creatorcontrib><creatorcontrib>YANG GUO-LIANG</creatorcontrib><title>Power semiconductor device having low gate input resistance</title><description>A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAOyC9PLVIoTs3NTM7PSylNLskvUkhJLctMTlXISCzLzEtXyMkvV0hPLElVyMwrKC1RKEotziwuScxLTuVhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhwRaG5haWRsZORsZEKAEAiiwvrQ</recordid><startdate>20120515</startdate><enddate>20120515</enddate><creator>LIAO SHIAN-HAU</creator><creator>LIN JIA-FU</creator><creator>LIN WEIIEH</creator><creator>YANG GUO-LIANG</creator><scope>EVB</scope></search><sort><creationdate>20120515</creationdate><title>Power semiconductor device having low gate input resistance</title><author>LIAO SHIAN-HAU ; LIN JIA-FU ; LIN WEIIEH ; YANG GUO-LIANG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8178923B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LIAO SHIAN-HAU</creatorcontrib><creatorcontrib>LIN JIA-FU</creatorcontrib><creatorcontrib>LIN WEIIEH</creatorcontrib><creatorcontrib>YANG GUO-LIANG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LIAO SHIAN-HAU</au><au>LIN JIA-FU</au><au>LIN WEIIEH</au><au>YANG GUO-LIANG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Power semiconductor device having low gate input resistance</title><date>2012-05-15</date><risdate>2012</risdate><abstract>A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Power semiconductor device having low gate input resistance
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T19%3A55%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LIAO%20SHIAN-HAU&rft.date=2012-05-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS8178923B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true