CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing lay...

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Hauptverfasser:	JAMMY RAJARAO, SUNG CHUN-YUNG, WISE RICHARD, ZHANG YING, IEONG MEIKEI, YAN HONGWEN, CHEN TZEIANG, KHARE MUKESH V
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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