Generating hardware accelerators and processor offloads

Generating hardware accelerators and processor offloads

System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a ha...

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Hauptverfasser: MOYER BRYON IRWIN, FRICKE STEPHEN JOHN JOSEPH, ATTIAS ROBERTO, DESHPANDE AKASH RENUKADAS, SINHA NAVENDU, GUPTA VINEET, SONAKIYA SHOBHIT, JORDAN WILLIAM CHARLES
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator MOYER BRYON IRWIN
FRICKE STEPHEN JOHN JOSEPH
ATTIAS ROBERTO
DESHPANDE AKASH RENUKADAS
SINHA NAVENDU
GUPTA VINEET
SONAKIYA SHOBHIT
JORDAN WILLIAM CHARLES
description System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.
format Patent
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Generating hardware accelerators and processor offloads
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