Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof
A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a ca...
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| creator | CHANG HSIAOUAN LEE HSU-YANG HU PINGNG CHIEN PAO-HUEI CHANG CHEN CHIEN-WEN LAI YI-SHAO TSAI TSUNG-YUEH |
| description | A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead. |
| format | Patent |
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In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20120214&DB=EPODOC&CC=US&NR=8115285B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20120214&DB=EPODOC&CC=US&NR=8115285B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHANG HSIAOUAN</creatorcontrib><creatorcontrib>LEE HSU-YANG</creatorcontrib><creatorcontrib>HU PINGNG</creatorcontrib><creatorcontrib>CHIEN PAO-HUEI CHANG</creatorcontrib><creatorcontrib>CHEN CHIEN-WEN</creatorcontrib><creatorcontrib>LAI YI-SHAO</creatorcontrib><creatorcontrib>TSAI TSUNG-YUEH</creatorcontrib><title>Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof</title><description>A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjUEKwjAQRbtxIeod5gIuWil0q6K4V9dlSCZNMZ3EZFJw5dVtxQO4-vzH4_9l8d7rEVmRhmdGDcahAHtwNBVl-wAB1QM7Aotjzx0ghOiFlPQjgcMXRRAPxHYegZSjwSkHn1m-OmsYkPNEJceZDCTW6wRiKZI362Jh0CXa_HJVwPl0O162FHxLaXonJmnv16Ys66qpD9XuD-UDGFpIlg</recordid><startdate>20120214</startdate><enddate>20120214</enddate><creator>CHANG HSIAOUAN</creator><creator>LEE HSU-YANG</creator><creator>HU PINGNG</creator><creator>CHIEN PAO-HUEI CHANG</creator><creator>CHEN CHIEN-WEN</creator><creator>LAI YI-SHAO</creator><creator>TSAI TSUNG-YUEH</creator><scope>EVB</scope></search><sort><creationdate>20120214</creationdate><title>Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof</title><author>CHANG HSIAOUAN ; LEE HSU-YANG ; HU PINGNG ; CHIEN PAO-HUEI CHANG ; CHEN CHIEN-WEN ; LAI YI-SHAO ; TSAI TSUNG-YUEH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8115285B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHANG HSIAOUAN</creatorcontrib><creatorcontrib>LEE HSU-YANG</creatorcontrib><creatorcontrib>HU PINGNG</creatorcontrib><creatorcontrib>CHIEN PAO-HUEI CHANG</creatorcontrib><creatorcontrib>CHEN CHIEN-WEN</creatorcontrib><creatorcontrib>LAI YI-SHAO</creatorcontrib><creatorcontrib>TSAI TSUNG-YUEH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHANG HSIAOUAN</au><au>LEE HSU-YANG</au><au>HU PINGNG</au><au>CHIEN PAO-HUEI CHANG</au><au>CHEN CHIEN-WEN</au><au>LAI YI-SHAO</au><au>TSAI TSUNG-YUEH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof</title><date>2012-02-14</date><risdate>2012</risdate><abstract>A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof |
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