Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same

Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodime...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	DIKSHIT ROHIT, GRUENHAGEN MICHAEL D, HO IHSIU, TJHIA EDDY, MURPHY JAMES J, WU CHUNG-LIN, KIM SUKU, LARSEN MARK
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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