Signal generator
Embodiments include a signal generator circuit for generating a time-varying signal, comprising capacitive element; FET to supply to or from the capacitive element a current matched to the FET drain current; a bias voltage generator to provide a bias voltage to the FET gate, wherein: the capacitance...
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| creator | GARNER DAVID M LALITHAMBIKA VINOD A |
| description | Embodiments include a signal generator circuit for generating a time-varying signal, comprising capacitive element; FET to supply to or from the capacitive element a current matched to the FET drain current; a bias voltage generator to provide a bias voltage to the FET gate, wherein: the capacitances per unit area of the capacitive element and the FET gate are matched; the bias voltage is substantially equal to a sum of a first voltage substantially proportional to a reference voltage and a second voltage substantially proportional to temperature; the FET source-gate voltage substantially equal to the sum of the bias voltage and the gate threshold voltage, the bias voltage and a further voltage approximately equal to the gate threshold voltage summed to determine the FET source-gate voltage, the circuit to control a time period of the time-varying signal dependent on the current supply. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US8022744B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US8022744B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US8022744B23</originalsourceid><addsrcrecordid>eNrjZBAIzkzPS8xRSE_NSy1KLMkv4mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFiclAlSXxocEWBkZG5iYmTkbGRCgBAHOIHwQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Signal generator</title><source>esp@cenet</source><creator>GARNER DAVID M ; LALITHAMBIKA VINOD A</creator><creatorcontrib>GARNER DAVID M ; LALITHAMBIKA VINOD A</creatorcontrib><description>Embodiments include a signal generator circuit for generating a time-varying signal, comprising capacitive element; FET to supply to or from the capacitive element a current matched to the FET drain current; a bias voltage generator to provide a bias voltage to the FET gate, wherein: the capacitances per unit area of the capacitive element and the FET gate are matched; the bias voltage is substantially equal to a sum of a first voltage substantially proportional to a reference voltage and a second voltage substantially proportional to temperature; the FET source-gate voltage substantially equal to the sum of the bias voltage and the gate threshold voltage, the bias voltage and a further voltage approximately equal to the gate threshold voltage summed to determine the FET source-gate voltage, the circuit to control a time period of the time-varying signal dependent on the current supply.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110920&DB=EPODOC&CC=US&NR=8022744B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110920&DB=EPODOC&CC=US&NR=8022744B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GARNER DAVID M</creatorcontrib><creatorcontrib>LALITHAMBIKA VINOD A</creatorcontrib><title>Signal generator</title><description>Embodiments include a signal generator circuit for generating a time-varying signal, comprising capacitive element; FET to supply to or from the capacitive element a current matched to the FET drain current; a bias voltage generator to provide a bias voltage to the FET gate, wherein: the capacitances per unit area of the capacitive element and the FET gate are matched; the bias voltage is substantially equal to a sum of a first voltage substantially proportional to a reference voltage and a second voltage substantially proportional to temperature; the FET source-gate voltage substantially equal to the sum of the bias voltage and the gate threshold voltage, the bias voltage and a further voltage approximately equal to the gate threshold voltage summed to determine the FET source-gate voltage, the circuit to control a time period of the time-varying signal dependent on the current supply.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAIzkzPS8xRSE_NSy1KLMkv4mFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFiclAlSXxocEWBkZG5iYmTkbGRCgBAHOIHwQ</recordid><startdate>20110920</startdate><enddate>20110920</enddate><creator>GARNER DAVID M</creator><creator>LALITHAMBIKA VINOD A</creator><scope>EVB</scope></search><sort><creationdate>20110920</creationdate><title>Signal generator</title><author>GARNER DAVID M ; LALITHAMBIKA VINOD A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US8022744B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>GARNER DAVID M</creatorcontrib><creatorcontrib>LALITHAMBIKA VINOD A</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GARNER DAVID M</au><au>LALITHAMBIKA VINOD A</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Signal generator</title><date>2011-09-20</date><risdate>2011</risdate><abstract>Embodiments include a signal generator circuit for generating a time-varying signal, comprising capacitive element; FET to supply to or from the capacitive element a current matched to the FET drain current; a bias voltage generator to provide a bias voltage to the FET gate, wherein: the capacitances per unit area of the capacitive element and the FET gate are matched; the bias voltage is substantially equal to a sum of a first voltage substantially proportional to a reference voltage and a second voltage substantially proportional to temperature; the FET source-gate voltage substantially equal to the sum of the bias voltage and the gate threshold voltage, the bias voltage and a further voltage approximately equal to the gate threshold voltage summed to determine the FET source-gate voltage, the circuit to control a time period of the time-varying signal dependent on the current supply.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
| title | Signal generator |
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