Low hydrogen concentration charge-trapping layer structures for non-volatile memory

Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	WU MIN-TA, LEE SHININ, HSIEH KUANG YEU, HSIEH JUNG-YU, LAI ERH-KUN, SHIH YEN-HAO
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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