Generating ROM bit cell arrays

A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each...

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Bibliographische Detailangaben

Hauptverfasser:	NEVERS YANNICK MARC, SCHUPPE VINCENT PHILIPPE
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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