Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same

Void boundary structures, semiconductor devices having the void boundary structures, and methods of forming the same are provided. The structures, semiconductor devices and methods present a way for reducing parasitic capacitance between interconnections by forming a void between the interconnection...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	YU CHEONG-SIK, LEE KYUNG-TAE
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
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