System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process

System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process

A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to crea...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: TUCKER DAVID, KUSHWAHA ASHISH, MOUTINHO THOMAS JAMES, DRIZLIKH SERGEI
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator TUCKER DAVID
KUSHWAHA ASHISH
MOUTINHO THOMAS JAMES
DRIZLIKH SERGEI
description A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7915093B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7915093B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7915093B13</originalsourceid><addsrcrecordid>eNqNjEEKwjAQRbtxIeod5gIFSxHpVlHcV9clpJM0pZ0JyQzi7c3CA7h68N_nbSvuP1lwBUMjrCgTj-A4wWpInbGiKZAvEgIJ-mQER7AhWQ1SVgm104xFgmWalawEJngHmcCAKPnSJoiLeoiJLea8rzbOLBkPP-4quN-e10eNkQfM0VgklOHVn7vmdOzaS9P-cfkCxtNDQA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process</title><source>esp@cenet</source><creator>TUCKER DAVID ; KUSHWAHA ASHISH ; MOUTINHO THOMAS JAMES ; DRIZLIKH SERGEI</creator><creatorcontrib>TUCKER DAVID ; KUSHWAHA ASHISH ; MOUTINHO THOMAS JAMES ; DRIZLIKH SERGEI</creatorcontrib><description>A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20110329&amp;DB=EPODOC&amp;CC=US&amp;NR=7915093B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20110329&amp;DB=EPODOC&amp;CC=US&amp;NR=7915093B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TUCKER DAVID</creatorcontrib><creatorcontrib>KUSHWAHA ASHISH</creatorcontrib><creatorcontrib>MOUTINHO THOMAS JAMES</creatorcontrib><creatorcontrib>DRIZLIKH SERGEI</creatorcontrib><title>System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process</title><description>A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjEEKwjAQRbtxIeod5gIFSxHpVlHcV9clpJM0pZ0JyQzi7c3CA7h68N_nbSvuP1lwBUMjrCgTj-A4wWpInbGiKZAvEgIJ-mQER7AhWQ1SVgm104xFgmWalawEJngHmcCAKPnSJoiLeoiJLea8rzbOLBkPP-4quN-e10eNkQfM0VgklOHVn7vmdOzaS9P-cfkCxtNDQA</recordid><startdate>20110329</startdate><enddate>20110329</enddate><creator>TUCKER DAVID</creator><creator>KUSHWAHA ASHISH</creator><creator>MOUTINHO THOMAS JAMES</creator><creator>DRIZLIKH SERGEI</creator><scope>EVB</scope></search><sort><creationdate>20110329</creationdate><title>System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process</title><author>TUCKER DAVID ; KUSHWAHA ASHISH ; MOUTINHO THOMAS JAMES ; DRIZLIKH SERGEI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7915093B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>TUCKER DAVID</creatorcontrib><creatorcontrib>KUSHWAHA ASHISH</creatorcontrib><creatorcontrib>MOUTINHO THOMAS JAMES</creatorcontrib><creatorcontrib>DRIZLIKH SERGEI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TUCKER DAVID</au><au>KUSHWAHA ASHISH</au><au>MOUTINHO THOMAS JAMES</au><au>DRIZLIKH SERGEI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process</title><date>2011-03-29</date><risdate>2011</risdate><abstract>A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US7915093B1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T10%3A02%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TUCKER%20DAVID&rft.date=2011-03-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7915093B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true