Accurate parasitics estimation for hierarchical customized VLSI design

Disclosed is a method of estimating interconnect wire parasitics in integrated circuits which includes obtaining a circuit layout having circuit components placed thereon including source input/output (I/O) pins and sink I/O pins, the circuit layout having a circuit hierarchy, bubbling up of the I/O...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	ROSE RONALD DENNIS, ZHOU JUN, CHAN YIU-HING
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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