Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers
An apparatus and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a pro...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | STARKE WILLIAM JOHN AL-OMARI RA'ED MOHAMMAD MERICAS ALEXANDER ERIK |
| description | An apparatus and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7913123B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7913123B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7913123B23</originalsourceid><addsrcrecordid>eNqNjbEOgkAQRGksjPoP-wMUQGFsJRp7tSbLuYckd7tk79DwM36riNpYWc1kZjJvnjxKYdOrEkc3QLiittwAgicvOoARjirOkQJ6mZqoaF6bTsVQCIB8ARZOf3IK0If315g0it5j7QhuI2Ey3Pt6vBU7UenyRd61jQR1by1pWCYziy7Q6qOLBPa7U3lIqZOKQoeGmGJ1Pq43WZHlxTYv_pg8AXzWVS0</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers</title><source>esp@cenet</source><creator>STARKE WILLIAM JOHN ; AL-OMARI RA'ED MOHAMMAD ; MERICAS ALEXANDER ERIK</creator><creatorcontrib>STARKE WILLIAM JOHN ; AL-OMARI RA'ED MOHAMMAD ; MERICAS ALEXANDER ERIK</creatorcontrib><description>An apparatus and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110322&DB=EPODOC&CC=US&NR=7913123B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110322&DB=EPODOC&CC=US&NR=7913123B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>STARKE WILLIAM JOHN</creatorcontrib><creatorcontrib>AL-OMARI RA'ED MOHAMMAD</creatorcontrib><creatorcontrib>MERICAS ALEXANDER ERIK</creatorcontrib><title>Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers</title><description>An apparatus and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjbEOgkAQRGksjPoP-wMUQGFsJRp7tSbLuYckd7tk79DwM36riNpYWc1kZjJvnjxKYdOrEkc3QLiittwAgicvOoARjirOkQJ6mZqoaF6bTsVQCIB8ARZOf3IK0If315g0it5j7QhuI2Ey3Pt6vBU7UenyRd61jQR1by1pWCYziy7Q6qOLBPa7U3lIqZOKQoeGmGJ1Pq43WZHlxTYv_pg8AXzWVS0</recordid><startdate>20110322</startdate><enddate>20110322</enddate><creator>STARKE WILLIAM JOHN</creator><creator>AL-OMARI RA'ED MOHAMMAD</creator><creator>MERICAS ALEXANDER ERIK</creator><scope>EVB</scope></search><sort><creationdate>20110322</creationdate><title>Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers</title><author>STARKE WILLIAM JOHN ; AL-OMARI RA'ED MOHAMMAD ; MERICAS ALEXANDER ERIK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7913123B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>STARKE WILLIAM JOHN</creatorcontrib><creatorcontrib>AL-OMARI RA'ED MOHAMMAD</creatorcontrib><creatorcontrib>MERICAS ALEXANDER ERIK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>STARKE WILLIAM JOHN</au><au>AL-OMARI RA'ED MOHAMMAD</au><au>MERICAS ALEXANDER ERIK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers</title><date>2011-03-22</date><risdate>2011</risdate><abstract>An apparatus and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US7913123B2 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T21%3A16%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=STARKE%20WILLIAM%20JOHN&rft.date=2011-03-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7913123B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |