Determining locations on a wafer to be reviewed during defect review

Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. The defects do not include defects d...

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Hauptverfasser:	SAIDIN ZAIN K, FOUQUET CHRISTOPHE, CHANG ELLIS, ABBOTT GORDON
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	SAIDIN ZAIN K FOUQUET CHRISTOPHE CHANG ELLIS ABBOTT GORDON
description	Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. The defects do not include defects detected on the wafer. The method also includes determining coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7904845B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7904845B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7904845B23</originalsourceid><addsrcrecordid>eNrjZHBxSS1JLcrNzMvMS1fIyU9OLMnMzytWyM9TSFQoT0xLLVIoyVdISlUoSi3LTC1PTVFIKS0CKU1JTUtNLoEK8zCwpiXmFKfyQmluBgU31xBnD93Ugvz41OKCxOTUvNSS-NBgc0sDEwsTUycjYyKUAAA9hjJn</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Determining locations on a wafer to be reviewed during defect review</title><source>esp@cenet</source><creator>SAIDIN ZAIN K ; FOUQUET CHRISTOPHE ; CHANG ELLIS ; ABBOTT GORDON</creator><creatorcontrib>SAIDIN ZAIN K ; FOUQUET CHRISTOPHE ; CHANG ELLIS ; ABBOTT GORDON</creatorcontrib><description>Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. The defects do not include defects detected on the wafer. The method also includes determining coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110308&DB=EPODOC&CC=US&NR=7904845B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110308&DB=EPODOC&CC=US&NR=7904845B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SAIDIN ZAIN K</creatorcontrib><creatorcontrib>FOUQUET CHRISTOPHE</creatorcontrib><creatorcontrib>CHANG ELLIS</creatorcontrib><creatorcontrib>ABBOTT GORDON</creatorcontrib><title>Determining locations on a wafer to be reviewed during defect review</title><description>Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. The defects do not include defects detected on the wafer. The method also includes determining coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHBxSS1JLcrNzMvMS1fIyU9OLMnMzytWyM9TSFQoT0xLLVIoyVdISlUoSi3LTC1PTVFIKS0CKU1JTUtNLoEK8zCwpiXmFKfyQmluBgU31xBnD93Ugvz41OKCxOTUvNSS-NBgc0sDEwsTUycjYyKUAAA9hjJn</recordid><startdate>20110308</startdate><enddate>20110308</enddate><creator>SAIDIN ZAIN K</creator><creator>FOUQUET CHRISTOPHE</creator><creator>CHANG ELLIS</creator><creator>ABBOTT GORDON</creator><scope>EVB</scope></search><sort><creationdate>20110308</creationdate><title>Determining locations on a wafer to be reviewed during defect review</title><author>SAIDIN ZAIN K ; FOUQUET CHRISTOPHE ; CHANG ELLIS ; ABBOTT GORDON</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7904845B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SAIDIN ZAIN K</creatorcontrib><creatorcontrib>FOUQUET CHRISTOPHE</creatorcontrib><creatorcontrib>CHANG ELLIS</creatorcontrib><creatorcontrib>ABBOTT GORDON</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SAIDIN ZAIN K</au><au>FOUQUET CHRISTOPHE</au><au>CHANG ELLIS</au><au>ABBOTT GORDON</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Determining locations on a wafer to be reviewed during defect review</title><date>2011-03-08</date><risdate>2011</risdate><abstract>Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. The defects do not include defects detected on the wafer. The method also includes determining coordinates of the locations on the wafer to be reviewed during the defect review by translating the coordinates of the defects into the coordinates on the wafer such that results of the defect review performed at the locations can be used to determine if the defects cause systematic defects on the wafer.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	Determining locations on a wafer to be reviewed during defect review
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-25T04%3A52%3A05IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SAIDIN%20ZAIN%20K&rft.date=2011-03-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7904845B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true