Embedded memory repair

A memory repair circuit for repairing one or more failures in an embedded memory includes at least one fuse register and state machine circuitry coupled to the fuse register. The state machine circuitry implements a first state machine operative: (i) to receive status information regarding the one or more failures in the embedded memory; (ii) to determine whether the memory is repairable based on the status information; (iii) when the memory is deemed repairable, to store an address corresponding to a failed memory cell of the memory; (iv) to burn the address corresponding to the failed memory cell into the fuse register using a voltage source supplied to the memory repair circuit; and (v) to verify that the address corresponding to the failed memory cell was burned into the fuse register. The state machine circuitry further implements a second state machine operative: (i) to download information stored in the at least one fuse register into at least one repair register associated with the embedded memory; and (ii) when an address is received in the circuit corresponding to a failed memory instance in the embedded memory, to reroute access to the failed memory instance to the at least one repair register.