Technique for patterning differently stressed layers formed above transistors by enhanced etch control strategies

During the patterning of stressed layers having different types of intrinsic stress, the effects of the deposition of a silicon dioxide based etch indicator material between the first and second dielectric layers may be significantly reduced by a controlled etch on the basis of optical measurement d...

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Hauptverfasser: MATTICK SYLVIO, SALZ HEIKE, RICHTER RALF, SCHALLER MATTHIAS
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creator MATTICK SYLVIO
SALZ HEIKE
RICHTER RALF
SCHALLER MATTHIAS
description During the patterning of stressed layers having different types of intrinsic stress, the effects of the deposition of a silicon dioxide based etch indicator material between the first and second dielectric layers may be significantly reduced by a controlled etch on the basis of optical measurement data indicating the etch rate and, thus, the performance of the respective etch process. In other cases, highly efficient etch indicator species may be incorporated into the stressed dielectric layers or may be formed on a surface portion thereof with reduced layer thickness, thereby providing an enhanced endpoint detection signal without creating the negative effects of silicon dioxide based indicator layers. In one illustrative embodiment, a stressed silicon, nitrogen and carbon-containing layer may be combined with a stressed silicon and nitrogen-containing layer, wherein the carbon species provides a prominent endpoint detection signal.
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subjects BASIC ELECTRIC ELEMENTS
CHEMICAL COMPOSITION OF GLASSES, GLAZES, OR VITREOUSENAMELS
CHEMISTRY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
GLASS
JOINING GLASS TO GLASS OR OTHER MATERIALS
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
METALLURGY
MINERAL OR SLAG WOOL
PHYSICS
SEMICONDUCTOR DEVICES
SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS,MINERALS OR SLAGS
SURFACE TREATMENT OF GLASS
TESTING
title Technique for patterning differently stressed layers formed above transistors by enhanced etch control strategies
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