System for using partitioned masks to build a chip
A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | OSTAPKO DANIEL L BHATTACHARYA SUBHRAJIT DARRINGER JOHN |
| description | A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a generic array type cell mask; and a custom blocking mask that includes blocking regions that positionally correspond with a set of IP components printed on a die. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7870531B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7870531B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7870531B23</originalsourceid><addsrcrecordid>eNrjZDAKriwuSc1VSMsvUigtzsxLVyhILCrJLMnMz0tNUchNLM4uVijJV0gqzcxJUUhUSM7ILOBhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhweYW5gamxoZORsZEKAEAZxMrlQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>System for using partitioned masks to build a chip</title><source>esp@cenet</source><creator>OSTAPKO DANIEL L ; BHATTACHARYA SUBHRAJIT ; DARRINGER JOHN</creator><creatorcontrib>OSTAPKO DANIEL L ; BHATTACHARYA SUBHRAJIT ; DARRINGER JOHN</creatorcontrib><description>A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a generic array type cell mask; and a custom blocking mask that includes blocking regions that positionally correspond with a set of IP components printed on a die.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110111&DB=EPODOC&CC=US&NR=7870531B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110111&DB=EPODOC&CC=US&NR=7870531B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OSTAPKO DANIEL L</creatorcontrib><creatorcontrib>BHATTACHARYA SUBHRAJIT</creatorcontrib><creatorcontrib>DARRINGER JOHN</creatorcontrib><title>System for using partitioned masks to build a chip</title><description>A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a generic array type cell mask; and a custom blocking mask that includes blocking regions that positionally correspond with a set of IP components printed on a die.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAKriwuSc1VSMsvUigtzsxLVyhILCrJLMnMz0tNUchNLM4uVijJV0gqzcxJUUhUSM7ILOBhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhweYW5gamxoZORsZEKAEAZxMrlQ</recordid><startdate>20110111</startdate><enddate>20110111</enddate><creator>OSTAPKO DANIEL L</creator><creator>BHATTACHARYA SUBHRAJIT</creator><creator>DARRINGER JOHN</creator><scope>EVB</scope></search><sort><creationdate>20110111</creationdate><title>System for using partitioned masks to build a chip</title><author>OSTAPKO DANIEL L ; BHATTACHARYA SUBHRAJIT ; DARRINGER JOHN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7870531B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>OSTAPKO DANIEL L</creatorcontrib><creatorcontrib>BHATTACHARYA SUBHRAJIT</creatorcontrib><creatorcontrib>DARRINGER JOHN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OSTAPKO DANIEL L</au><au>BHATTACHARYA SUBHRAJIT</au><au>DARRINGER JOHN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>System for using partitioned masks to build a chip</title><date>2011-01-11</date><risdate>2011</risdate><abstract>A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a generic array type cell mask; and a custom blocking mask that includes blocking regions that positionally correspond with a set of IP components printed on a die.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US7870531B2 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | System for using partitioned masks to build a chip |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T05%3A50%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=OSTAPKO%20DANIEL%20L&rft.date=2011-01-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7870531B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |