Test interface for memory elements

A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port o...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	BUETTNER STEFAN, PILLE JUERGEN, BRANDT UWE, JUCHMES WERNER
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS STATIC STORES TESTING
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