Non-volatile memory with reduced charge fluence

Non-volatile memory with reduced charge fluence

A method including performing a program/erase cycle on a first non-volatile memory (NVM) bit of an integrated circuit using a first fluence, wherein the first NVM bit has a first transconductance is provided. The method further includes performing a program/erase cycle on a second NVM bit of the int...

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1. Verfasser: SYZDEK RONALD J
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Sprache:eng
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INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator SYZDEK RONALD J
description A method including performing a program/erase cycle on a first non-volatile memory (NVM) bit of an integrated circuit using a first fluence, wherein the first NVM bit has a first transconductance is provided. The method further includes performing a program/erase cycle on a second NVM bit of the integrated circuit using a second fluence, wherein the second NVM bit has a second transconductance, and wherein the first transconductance is greater than the second transconductance and the second fluence is greater than the first fluence.
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subjects INFORMATION STORAGE
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STATIC STORES
title Non-volatile memory with reduced charge fluence
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