Semiconductor layout design apparatus and method for evaluating a floorplan using distances between standard cells and macrocells

A semiconductor layout design apparatus has an inter-block connection information extracting part, a cell initial placement part and an evaluation value. The inter-block connection information extracting part configured to extract the number of wiring connections between a plurality of blocks includ...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SEKINE MIZUE, WANG SHEN, UTSUMI TETSUAKI
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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