Test structures and methods
Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a...
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| creator | MAROKKEY SAJAN |
| description | Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece. |
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In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20101026&DB=EPODOC&CC=US&NR=7820458B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20101026&DB=EPODOC&CC=US&NR=7820458B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MAROKKEY SAJAN</creatorcontrib><title>Test structures and methods</title><description>Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAOSS0uUSguKSpNLiktSi1WSMxLUchNLcnITynmYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxocHmFkYGJqYWTkbGRCgBAEpUI2M</recordid><startdate>20101026</startdate><enddate>20101026</enddate><creator>MAROKKEY SAJAN</creator><scope>EVB</scope></search><sort><creationdate>20101026</creationdate><title>Test structures and methods</title><author>MAROKKEY SAJAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7820458B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>MAROKKEY SAJAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MAROKKEY SAJAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Test structures and methods</title><date>2010-10-26</date><risdate>2010</risdate><abstract>Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING |
| title | Test structures and methods |
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