Methods for forming contacts for dual stress liner CMOS semiconductor devices
Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | KU JA HUM PARK WANJAE STANDAERT THEODORUS E CHANG CHONG KWANG LEE KYOUNG WOO |
| description | Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7816271B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7816271B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7816271B23</originalsourceid><addsrcrecordid>eNrjZPD1TS3JyE8pVkjLLwLh3My8dIXk_LySxOQSiGBKaWKOQnFJUWpxsUJOZl5qkYKzr3-wQnFqbiZQXUppcglIUWpZZnJqMQ8Da1piTnEqL5TmZlBwcw1x9tBNLciPTy0uSExOzUstiQ8NNrcwNDMyN3QyMiZCCQBt0DXx</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Methods for forming contacts for dual stress liner CMOS semiconductor devices</title><source>esp@cenet</source><creator>KU JA HUM ; PARK WANJAE ; STANDAERT THEODORUS E ; CHANG CHONG KWANG ; LEE KYOUNG WOO</creator><creatorcontrib>KU JA HUM ; PARK WANJAE ; STANDAERT THEODORUS E ; CHANG CHONG KWANG ; LEE KYOUNG WOO</creatorcontrib><description>Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20101019&DB=EPODOC&CC=US&NR=7816271B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20101019&DB=EPODOC&CC=US&NR=7816271B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KU JA HUM</creatorcontrib><creatorcontrib>PARK WANJAE</creatorcontrib><creatorcontrib>STANDAERT THEODORUS E</creatorcontrib><creatorcontrib>CHANG CHONG KWANG</creatorcontrib><creatorcontrib>LEE KYOUNG WOO</creatorcontrib><title>Methods for forming contacts for dual stress liner CMOS semiconductor devices</title><description>Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPD1TS3JyE8pVkjLLwLh3My8dIXk_LySxOQSiGBKaWKOQnFJUWpxsUJOZl5qkYKzr3-wQnFqbiZQXUppcglIUWpZZnJqMQ8Da1piTnEqL5TmZlBwcw1x9tBNLciPTy0uSExOzUstiQ8NNrcwNDMyN3QyMiZCCQBt0DXx</recordid><startdate>20101019</startdate><enddate>20101019</enddate><creator>KU JA HUM</creator><creator>PARK WANJAE</creator><creator>STANDAERT THEODORUS E</creator><creator>CHANG CHONG KWANG</creator><creator>LEE KYOUNG WOO</creator><scope>EVB</scope></search><sort><creationdate>20101019</creationdate><title>Methods for forming contacts for dual stress liner CMOS semiconductor devices</title><author>KU JA HUM ; PARK WANJAE ; STANDAERT THEODORUS E ; CHANG CHONG KWANG ; LEE KYOUNG WOO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7816271B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KU JA HUM</creatorcontrib><creatorcontrib>PARK WANJAE</creatorcontrib><creatorcontrib>STANDAERT THEODORUS E</creatorcontrib><creatorcontrib>CHANG CHONG KWANG</creatorcontrib><creatorcontrib>LEE KYOUNG WOO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KU JA HUM</au><au>PARK WANJAE</au><au>STANDAERT THEODORUS E</au><au>CHANG CHONG KWANG</au><au>LEE KYOUNG WOO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Methods for forming contacts for dual stress liner CMOS semiconductor devices</title><date>2010-10-19</date><risdate>2010</risdate><abstract>Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US7816271B2 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Methods for forming contacts for dual stress liner CMOS semiconductor devices |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T06%3A59%3A30IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KU%20JA%20HUM&rft.date=2010-10-19&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7816271B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |