Memory chip for high capacity memory subsystem supporting multiple speed bus

A memory module contains an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Pr...

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Bibliographische Detailangaben

Hauptverfasser:	BARTLEY GERALD KEITH, BORKENHAGEN JOHN MICHAEL, GERMANN PHILIP RAYMOND
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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