Memory chip for high capacity memory subsystem supporting multiple speed bus

A memory module contains an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.