Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readings

Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided. The memor...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	KOEBERNIK GERT, RICHTER DETLEV, VEREDAS RAMIREZ XAVIER, RAVASIO ROBERTO, REISSMANN MIRKO, GALLO GIROLAMO
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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