Wafer cutting methods and packages using dice derived therefrom

A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes second cutting the semiconductive wafer along a second path at a given second cutting intensity. The second...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: DYDYK MARK, POONJOLAI ERASENTHIRAN
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator DYDYK MARK
POONJOLAI ERASENTHIRAN
description A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes second cutting the semiconductive wafer along a second path at a given second cutting intensity. The second cutting intensity is diminished during crossing the intersection and resumed to the given cutting intensity after crossing the intersection.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7795116B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7795116B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7795116B23</originalsourceid><addsrcrecordid>eNrjZLAPT0xLLVJILi0pycxLV8hNLcnITylWSMxLUShITM5OTE8tVigtBkmlZCanKqSkFmWWpaYolGSkFqWmFeXn8jCwpiXmFKfyQmluBgU31xBnD93Ugvz41GKgGal5qSXxocHm5pamhoZmTkbGRCgBADWHMMM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Wafer cutting methods and packages using dice derived therefrom</title><source>esp@cenet</source><creator>DYDYK MARK ; POONJOLAI ERASENTHIRAN</creator><creatorcontrib>DYDYK MARK ; POONJOLAI ERASENTHIRAN</creatorcontrib><description>A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes second cutting the semiconductive wafer along a second path at a given second cutting intensity. The second cutting intensity is diminished during crossing the intersection and resumed to the given cutting intensity after crossing the intersection.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CLADDING OR PLATING BY SOLDERING OR WELDING ; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MACHINE TOOLS ; METAL-WORKING NOT OTHERWISE PROVIDED FOR ; PERFORMING OPERATIONS ; SEMICONDUCTOR DEVICES ; SOLDERING OR UNSOLDERING ; TRANSPORTING ; WELDING ; WORKING BY LASER BEAM</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20100914&amp;DB=EPODOC&amp;CC=US&amp;NR=7795116B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20100914&amp;DB=EPODOC&amp;CC=US&amp;NR=7795116B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DYDYK MARK</creatorcontrib><creatorcontrib>POONJOLAI ERASENTHIRAN</creatorcontrib><title>Wafer cutting methods and packages using dice derived therefrom</title><description>A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes second cutting the semiconductive wafer along a second path at a given second cutting intensity. The second cutting intensity is diminished during crossing the intersection and resumed to the given cutting intensity after crossing the intersection.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CLADDING OR PLATING BY SOLDERING OR WELDING</subject><subject>CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MACHINE TOOLS</subject><subject>METAL-WORKING NOT OTHERWISE PROVIDED FOR</subject><subject>PERFORMING OPERATIONS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>SOLDERING OR UNSOLDERING</subject><subject>TRANSPORTING</subject><subject>WELDING</subject><subject>WORKING BY LASER BEAM</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAPT0xLLVJILi0pycxLV8hNLcnITylWSMxLUShITM5OTE8tVigtBkmlZCanKqSkFmWWpaYolGSkFqWmFeXn8jCwpiXmFKfyQmluBgU31xBnD93Ugvz41GKgGal5qSXxocHm5pamhoZmTkbGRCgBADWHMMM</recordid><startdate>20100914</startdate><enddate>20100914</enddate><creator>DYDYK MARK</creator><creator>POONJOLAI ERASENTHIRAN</creator><scope>EVB</scope></search><sort><creationdate>20100914</creationdate><title>Wafer cutting methods and packages using dice derived therefrom</title><author>DYDYK MARK ; POONJOLAI ERASENTHIRAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7795116B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CLADDING OR PLATING BY SOLDERING OR WELDING</topic><topic>CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MACHINE TOOLS</topic><topic>METAL-WORKING NOT OTHERWISE PROVIDED FOR</topic><topic>PERFORMING OPERATIONS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>SOLDERING OR UNSOLDERING</topic><topic>TRANSPORTING</topic><topic>WELDING</topic><topic>WORKING BY LASER BEAM</topic><toplevel>online_resources</toplevel><creatorcontrib>DYDYK MARK</creatorcontrib><creatorcontrib>POONJOLAI ERASENTHIRAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DYDYK MARK</au><au>POONJOLAI ERASENTHIRAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Wafer cutting methods and packages using dice derived therefrom</title><date>2010-09-14</date><risdate>2010</risdate><abstract>A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes second cutting the semiconductive wafer along a second path at a given second cutting intensity. The second cutting intensity is diminished during crossing the intersection and resumed to the given cutting intensity after crossing the intersection.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US7795116B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
CLADDING OR PLATING BY SOLDERING OR WELDING
CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MACHINE TOOLS
METAL-WORKING NOT OTHERWISE PROVIDED FOR
PERFORMING OPERATIONS
SEMICONDUCTOR DEVICES
SOLDERING OR UNSOLDERING
TRANSPORTING
WELDING
WORKING BY LASER BEAM
title Wafer cutting methods and packages using dice derived therefrom
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T17%3A06%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=DYDYK%20MARK&rft.date=2010-09-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7795116B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true