Methods for charge dissipation in integrated circuits

Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrica...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: DEVRIES KENNETH L, RUNYON STEPHEN LARRY, GRECO NANCY ANNE, PRESTON JOAN
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator DEVRIES KENNETH L
RUNYON STEPHEN LARRY
GRECO NANCY ANNE
PRESTON JOAN
description Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7759173B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7759173B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7759173B23</originalsourceid><addsrcrecordid>eNrjZDD1TS3JyE8pVkjLL1JIzkgsSk9VSMksLs4sSCzJzM9TyAShktT0osSS1BSF5Myi5NLMkmIeBta0xJziVF4ozc2g4OYa4uyhm1qQH59aXJCYnJqXWhIfGmxubmppaG7sZGRMhBIALqItTA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Methods for charge dissipation in integrated circuits</title><source>esp@cenet</source><creator>DEVRIES KENNETH L ; RUNYON STEPHEN LARRY ; GRECO NANCY ANNE ; PRESTON JOAN</creator><creatorcontrib>DEVRIES KENNETH L ; RUNYON STEPHEN LARRY ; GRECO NANCY ANNE ; PRESTON JOAN</creatorcontrib><description>Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20100720&amp;DB=EPODOC&amp;CC=US&amp;NR=7759173B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20100720&amp;DB=EPODOC&amp;CC=US&amp;NR=7759173B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DEVRIES KENNETH L</creatorcontrib><creatorcontrib>RUNYON STEPHEN LARRY</creatorcontrib><creatorcontrib>GRECO NANCY ANNE</creatorcontrib><creatorcontrib>PRESTON JOAN</creatorcontrib><title>Methods for charge dissipation in integrated circuits</title><description>Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD1TS3JyE8pVkjLL1JIzkgsSk9VSMksLs4sSCzJzM9TyAShktT0osSS1BSF5Myi5NLMkmIeBta0xJziVF4ozc2g4OYa4uyhm1qQH59aXJCYnJqXWhIfGmxubmppaG7sZGRMhBIALqItTA</recordid><startdate>20100720</startdate><enddate>20100720</enddate><creator>DEVRIES KENNETH L</creator><creator>RUNYON STEPHEN LARRY</creator><creator>GRECO NANCY ANNE</creator><creator>PRESTON JOAN</creator><scope>EVB</scope></search><sort><creationdate>20100720</creationdate><title>Methods for charge dissipation in integrated circuits</title><author>DEVRIES KENNETH L ; RUNYON STEPHEN LARRY ; GRECO NANCY ANNE ; PRESTON JOAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7759173B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>DEVRIES KENNETH L</creatorcontrib><creatorcontrib>RUNYON STEPHEN LARRY</creatorcontrib><creatorcontrib>GRECO NANCY ANNE</creatorcontrib><creatorcontrib>PRESTON JOAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DEVRIES KENNETH L</au><au>RUNYON STEPHEN LARRY</au><au>GRECO NANCY ANNE</au><au>PRESTON JOAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Methods for charge dissipation in integrated circuits</title><date>2010-07-20</date><risdate>2010</risdate><abstract>Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US7759173B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Methods for charge dissipation in integrated circuits
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T11%3A24%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=DEVRIES%20KENNETH%20L&rft.date=2010-07-20&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7759173B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true