Fractional-N phased-lock-loop (PLL) system
In one general embodiment, a fractional-N phased-lock-loop (PLL) structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled osc...
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| creator | FENG KAI DI |
| description | In one general embodiment, a fractional-N phased-lock-loop (PLL) structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. Additional systems and structures are also presented. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7750697B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7750697B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7750697B23</originalsourceid><addsrcrecordid>eNrjZNByK0pMLsnMz0vM0fVTKMhILE5N0c3JT84GEvkFChoBPj6aCsWVxSWpuTwMrGmJOcWpvFCam0HBzTXE2UM3tSA_PrW4IDE5NS-1JD402Nzc1MDM0tzJyJgIJQCBZifj</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Fractional-N phased-lock-loop (PLL) system</title><source>esp@cenet</source><creator>FENG KAI DI</creator><creatorcontrib>FENG KAI DI</creatorcontrib><description>In one general embodiment, a fractional-N phased-lock-loop (PLL) structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. Additional systems and structures are also presented.</description><language>eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100706&DB=EPODOC&CC=US&NR=7750697B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100706&DB=EPODOC&CC=US&NR=7750697B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FENG KAI DI</creatorcontrib><title>Fractional-N phased-lock-loop (PLL) system</title><description>In one general embodiment, a fractional-N phased-lock-loop (PLL) structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. Additional systems and structures are also presented.</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNByK0pMLsnMz0vM0fVTKMhILE5N0c3JT84GEvkFChoBPj6aCsWVxSWpuTwMrGmJOcWpvFCam0HBzTXE2UM3tSA_PrW4IDE5NS-1JD402Nzc1MDM0tzJyJgIJQCBZifj</recordid><startdate>20100706</startdate><enddate>20100706</enddate><creator>FENG KAI DI</creator><scope>EVB</scope></search><sort><creationdate>20100706</creationdate><title>Fractional-N phased-lock-loop (PLL) system</title><author>FENG KAI DI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7750697B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>FENG KAI DI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FENG KAI DI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Fractional-N phased-lock-loop (PLL) system</title><date>2010-07-06</date><risdate>2010</risdate><abstract>In one general embodiment, a fractional-N phased-lock-loop (PLL) structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. Additional systems and structures are also presented.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY |
| title | Fractional-N phased-lock-loop (PLL) system |
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