Hybrid analog/digital phase-lock loop for low-jitter synchronization

A hybrid analog/digital phase-lock loop for low-jitter synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level. A numerically-controlled analog oscillator provides a clock output and has an input for receiving a rational number. The...

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Bibliographische Detailangaben

Hauptverfasser:	YOU ZHONG, GREEN STEVEN RANDALL, MELANSON JOHN L, WOODFORD SCOTT ALLAN
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER ELECTRICITY
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