Chip circuit for combined and data compressed FIFO arbitration for a non-blocking switch

Chip circuit for combined and data compressed FIFO arbitration for a non-blocking switch

A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control...

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Hauptverfasser: ABEL FRANCOIS, HOLM INGEMAR, KOHLER HELMUT, SCHUMACHER NORBERT, GOLDRIAN GOTTFRIED ANDREAS
Format: Patent
Sprache:eng
Schlagworte:
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
MULTIPLEX COMMUNICATION
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator ABEL FRANCOIS
HOLM INGEMAR
KOHLER HELMUT
SCHUMACHER NORBERT
GOLDRIAN GOTTFRIED ANDREAS
description A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.
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subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
MULTIPLEX COMMUNICATION
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title Chip circuit for combined and data compressed FIFO arbitration for a non-blocking switch
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