Integrated matching networks and RF devices that include an integrated matching network
An integrated matching network includes a first die on a substrate, a second die on the substrate, and a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedanc...
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creator | FOERSTNER JUERGEN A MILLER MELVY F |
description | An integrated matching network includes a first die on a substrate, a second die on the substrate, and a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a power amplifier, a second die having a capacitor, and a metal interconnect coupled to the power amplifier and the first capacitor. The metal interconnect has an inductance. The capacitor and metal interconnect form a shunt impedance. |
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The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a power amplifier, a second die having a capacitor, and a metal interconnect coupled to the power amplifier and the first capacitor. The metal interconnect has an inductance. The capacitor and metal interconnect form a shunt impedance.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100223&DB=EPODOC&CC=US&NR=7667334B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100223&DB=EPODOC&CC=US&NR=7667334B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FOERSTNER JUERGEN A</creatorcontrib><creatorcontrib>MILLER MELVY F</creatorcontrib><title>Integrated matching networks and RF devices that include an integrated matching network</title><description>An integrated matching network includes a first die on a substrate, a second die on the substrate, and a metallization layer on the first and second dies. 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The capacitor and metal interconnect form a shunt impedance.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAj3zCtJTS9KLElNUchNLEnOyMxLV8hLLSnPL8ouVkjMS1EIclNISS3LTE4tVijJSCxRyMxLzilNSQXKAZk49fIwsKYl5hSn8kJpbgYFN9cQZw_d1IL8-NTigsTkVKDK-NBgczMzc2NjEycjYyKUAAD3CDnV</recordid><startdate>20100223</startdate><enddate>20100223</enddate><creator>FOERSTNER JUERGEN A</creator><creator>MILLER MELVY F</creator><scope>EVB</scope></search><sort><creationdate>20100223</creationdate><title>Integrated matching networks and RF devices that include an integrated matching network</title><author>FOERSTNER JUERGEN A ; MILLER MELVY F</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7667334B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>FOERSTNER JUERGEN A</creatorcontrib><creatorcontrib>MILLER MELVY F</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FOERSTNER JUERGEN A</au><au>MILLER MELVY F</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated matching networks and RF devices that include an integrated matching network</title><date>2010-02-23</date><risdate>2010</risdate><abstract>An integrated matching network includes a first die on a substrate, a second die on the substrate, and a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a power amplifier, a second die having a capacitor, and a metal interconnect coupled to the power amplifier and the first capacitor. The metal interconnect has an inductance. The capacitor and metal interconnect form a shunt impedance.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Integrated matching networks and RF devices that include an integrated matching network |
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