Direct digital synthesis circuit
A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical mul...
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creator | HOLLENBECK NEAL W RAKERS PATRICK L BUSHMAN MICHAEL L |
description | A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents. |
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The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.</description><language>eng</language><subject>ANALOGUE COMPUTERS ; CALCULATING ; COMPUTING ; COUNTING ; PHYSICS</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100126&DB=EPODOC&CC=US&NR=7653678B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100126&DB=EPODOC&CC=US&NR=7653678B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HOLLENBECK NEAL W</creatorcontrib><creatorcontrib>RAKERS PATRICK L</creatorcontrib><creatorcontrib>BUSHMAN MICHAEL L</creatorcontrib><title>Direct digital synthesis circuit</title><description>A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.</description><subject>ANALOGUE COMPUTERS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBwySxKTS5RSMlMzyxJzFEorswryUgtzixWSM4sSi7NLOFhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGhweZmpsZm5hZORsZEKAEAKcAlYw</recordid><startdate>20100126</startdate><enddate>20100126</enddate><creator>HOLLENBECK NEAL W</creator><creator>RAKERS PATRICK L</creator><creator>BUSHMAN MICHAEL L</creator><scope>EVB</scope></search><sort><creationdate>20100126</creationdate><title>Direct digital synthesis circuit</title><author>HOLLENBECK NEAL W ; RAKERS PATRICK L ; BUSHMAN MICHAEL L</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7653678B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>ANALOGUE COMPUTERS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>HOLLENBECK NEAL W</creatorcontrib><creatorcontrib>RAKERS PATRICK L</creatorcontrib><creatorcontrib>BUSHMAN MICHAEL L</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HOLLENBECK NEAL W</au><au>RAKERS PATRICK L</au><au>BUSHMAN MICHAEL L</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Direct digital synthesis circuit</title><date>2010-01-26</date><risdate>2010</risdate><abstract>A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | ANALOGUE COMPUTERS CALCULATING COMPUTING COUNTING PHYSICS |
title | Direct digital synthesis circuit |
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