System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation

A system and method processor testing using test pattern re-execution is presented. A processor re-executes test patterns using different timing scenarios in order to reduce test pattern build time and increase system test coverage. The invention described herein varies initial states of a processor...

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Bibliographische Detailangaben

Hauptverfasser:	HATTI SUNIL SURESH, NANJUNDIAH BHAVANI SHRINGARI, DUSANAPUDI MANOJ, BUSSA VINOD, MOHARIL RAHUL SHARAD, KAPOOR SHAKTI
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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