Memory cell with single-event-upset tolerance

A memory cell having a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value has an aspect ratio of at least 5:1. The high aspect ratio provides adequate spacing between nodes of the memory cel...

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Hauptverfasser: NGUYEN SUSAN XUAN, DE JONG JAN L, PANG RAYMOND C
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creator NGUYEN SUSAN XUAN
DE JONG JAN L
PANG RAYMOND C
description A memory cell having a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value has an aspect ratio of at least 5:1. The high aspect ratio provides adequate spacing between nodes of the memory cell for SEU tolerance at small design technologies.
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Memory cell with single-event-upset tolerance
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