Method for fabricating an integrated gate dielectric layer for field effect transistors

Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and therm...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	CHUA THAI CHENG, URITSKY YURI, CONTI GIUSEPPINA, SWENBERG JOHANES, WANG CHIKUANG CHARLES, MUTHUKRISNAN SHANKAR, KHER SHREYAS
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	CHUA THAI CHENG URITSKY YURI CONTI GIUSEPPINA SWENBERG JOHANES WANG CHIKUANG CHARLES MUTHUKRISNAN SHANKAR KHER SHREYAS
description	Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7601648B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7601648B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7601648B23</originalsourceid><addsrcrecordid>eNqNiz0KQjEQhNNYiHqHvYDgH09rRbGxUrF8rMkkBkLy2Gzj7Q3oAWxmYL5vxuZxgb6KI1-EPD8lWtaYA3GmmBVBWOEotCQXkWC1KZT4Dfl-2ugI3jdCKpxrrFqkTs3Ic6qY_Xpi6HS8Hc5zDKVHHdgiQ_v7ddstlt1mt1-t_1A-9aU54g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for fabricating an integrated gate dielectric layer for field effect transistors</title><source>esp@cenet</source><creator>CHUA THAI CHENG ; URITSKY YURI ; CONTI GIUSEPPINA ; SWENBERG JOHANES ; WANG CHIKUANG CHARLES ; MUTHUKRISNAN SHANKAR ; KHER SHREYAS</creator><creatorcontrib>CHUA THAI CHENG ; URITSKY YURI ; CONTI GIUSEPPINA ; SWENBERG JOHANES ; WANG CHIKUANG CHARLES ; MUTHUKRISNAN SHANKAR ; KHER SHREYAS</creatorcontrib><description>Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2009</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20091013&DB=EPODOC&CC=US&NR=7601648B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20091013&DB=EPODOC&CC=US&NR=7601648B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHUA THAI CHENG</creatorcontrib><creatorcontrib>URITSKY YURI</creatorcontrib><creatorcontrib>CONTI GIUSEPPINA</creatorcontrib><creatorcontrib>SWENBERG JOHANES</creatorcontrib><creatorcontrib>WANG CHIKUANG CHARLES</creatorcontrib><creatorcontrib>MUTHUKRISNAN SHANKAR</creatorcontrib><creatorcontrib>KHER SHREYAS</creatorcontrib><title>Method for fabricating an integrated gate dielectric layer for field effect transistors</title><description>Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNiz0KQjEQhNNYiHqHvYDgH09rRbGxUrF8rMkkBkLy2Gzj7Q3oAWxmYL5vxuZxgb6KI1-EPD8lWtaYA3GmmBVBWOEotCQXkWC1KZT4Dfl-2ugI3jdCKpxrrFqkTs3Ic6qY_Xpi6HS8Hc5zDKVHHdgiQ_v7ddstlt1mt1-t_1A-9aU54g</recordid><startdate>20091013</startdate><enddate>20091013</enddate><creator>CHUA THAI CHENG</creator><creator>URITSKY YURI</creator><creator>CONTI GIUSEPPINA</creator><creator>SWENBERG JOHANES</creator><creator>WANG CHIKUANG CHARLES</creator><creator>MUTHUKRISNAN SHANKAR</creator><creator>KHER SHREYAS</creator><scope>EVB</scope></search><sort><creationdate>20091013</creationdate><title>Method for fabricating an integrated gate dielectric layer for field effect transistors</title><author>CHUA THAI CHENG ; URITSKY YURI ; CONTI GIUSEPPINA ; SWENBERG JOHANES ; WANG CHIKUANG CHARLES ; MUTHUKRISNAN SHANKAR ; KHER SHREYAS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7601648B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2009</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHUA THAI CHENG</creatorcontrib><creatorcontrib>URITSKY YURI</creatorcontrib><creatorcontrib>CONTI GIUSEPPINA</creatorcontrib><creatorcontrib>SWENBERG JOHANES</creatorcontrib><creatorcontrib>WANG CHIKUANG CHARLES</creatorcontrib><creatorcontrib>MUTHUKRISNAN SHANKAR</creatorcontrib><creatorcontrib>KHER SHREYAS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHUA THAI CHENG</au><au>URITSKY YURI</au><au>CONTI GIUSEPPINA</au><au>SWENBERG JOHANES</au><au>WANG CHIKUANG CHARLES</au><au>MUTHUKRISNAN SHANKAR</au><au>KHER SHREYAS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for fabricating an integrated gate dielectric layer for field effect transistors</title><date>2009-10-13</date><risdate>2009</risdate><abstract>Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US7601648B2
source	esp@cenet
subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	Method for fabricating an integrated gate dielectric layer for field effect transistors
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-13T13%3A05%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHUA%20THAI%20CHENG&rft.date=2009-10-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7601648B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true