System for expanding a window of valid data
In one general embodiment, a design structure is provided including a first delay line having at least one buffer, the first delay line being for shifting a clock, a second delay line having at least one buffer, the second delay line being for shifting data, and a logic block adapted to identify a p...
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| creator | MILTON DAVID WILLS KUEMERLE MARK WILLIAM BERHANU MALEDE WONDMAGEGNE SMITH JACK ROBERT OGILVIE CLARENCE ROSSER HANUDEL CHRISTOPHER DOUGLAS |
| description | In one general embodiment, a design structure is provided including a first delay line having at least one buffer, the first delay line being for shifting a clock, a second delay line having at least one buffer, the second delay line being for shifting data, and a logic block adapted to identify a predetermined section of a data window. Additionally, the logic block monitors a clock signal along predetermined portions of the delay line to identify the predetermined section of the data window. Once the predetermined section of the data window is identified the logic block forwards the data associated with the predetermined section to an output pin, with the proviso that no memory element is present, and with the proviso that no feedback line is present. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7529962B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7529962B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7529962B13</originalsourceid><addsrcrecordid>eNrjZNAOriwuSc1VSMsvUkitKEjMS8nMS1dIVCjPzEvJL1fIT1MoS8zJTFFISSxJ5GFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHB5qZGlpZmRk6GxkQoAQDv_CjU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>System for expanding a window of valid data</title><source>esp@cenet</source><creator>MILTON DAVID WILLS ; KUEMERLE MARK WILLIAM ; BERHANU MALEDE WONDMAGEGNE ; SMITH JACK ROBERT ; OGILVIE CLARENCE ROSSER ; HANUDEL CHRISTOPHER DOUGLAS</creator><creatorcontrib>MILTON DAVID WILLS ; KUEMERLE MARK WILLIAM ; BERHANU MALEDE WONDMAGEGNE ; SMITH JACK ROBERT ; OGILVIE CLARENCE ROSSER ; HANUDEL CHRISTOPHER DOUGLAS</creatorcontrib><description>In one general embodiment, a design structure is provided including a first delay line having at least one buffer, the first delay line being for shifting a clock, a second delay line having at least one buffer, the second delay line being for shifting data, and a logic block adapted to identify a predetermined section of a data window. Additionally, the logic block monitors a clock signal along predetermined portions of the delay line to identify the predetermined section of the data window. Once the predetermined section of the data window is identified the logic block forwards the data associated with the predetermined section to an output pin, with the proviso that no memory element is present, and with the proviso that no feedback line is present.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2009</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090505&DB=EPODOC&CC=US&NR=7529962B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090505&DB=EPODOC&CC=US&NR=7529962B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MILTON DAVID WILLS</creatorcontrib><creatorcontrib>KUEMERLE MARK WILLIAM</creatorcontrib><creatorcontrib>BERHANU MALEDE WONDMAGEGNE</creatorcontrib><creatorcontrib>SMITH JACK ROBERT</creatorcontrib><creatorcontrib>OGILVIE CLARENCE ROSSER</creatorcontrib><creatorcontrib>HANUDEL CHRISTOPHER DOUGLAS</creatorcontrib><title>System for expanding a window of valid data</title><description>In one general embodiment, a design structure is provided including a first delay line having at least one buffer, the first delay line being for shifting a clock, a second delay line having at least one buffer, the second delay line being for shifting data, and a logic block adapted to identify a predetermined section of a data window. Additionally, the logic block monitors a clock signal along predetermined portions of the delay line to identify the predetermined section of the data window. Once the predetermined section of the data window is identified the logic block forwards the data associated with the predetermined section to an output pin, with the proviso that no memory element is present, and with the proviso that no feedback line is present.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAOriwuSc1VSMsvUkitKEjMS8nMS1dIVCjPzEvJL1fIT1MoS8zJTFFISSxJ5GFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8aHB5qZGlpZmRk6GxkQoAQDv_CjU</recordid><startdate>20090505</startdate><enddate>20090505</enddate><creator>MILTON DAVID WILLS</creator><creator>KUEMERLE MARK WILLIAM</creator><creator>BERHANU MALEDE WONDMAGEGNE</creator><creator>SMITH JACK ROBERT</creator><creator>OGILVIE CLARENCE ROSSER</creator><creator>HANUDEL CHRISTOPHER DOUGLAS</creator><scope>EVB</scope></search><sort><creationdate>20090505</creationdate><title>System for expanding a window of valid data</title><author>MILTON DAVID WILLS ; KUEMERLE MARK WILLIAM ; BERHANU MALEDE WONDMAGEGNE ; SMITH JACK ROBERT ; OGILVIE CLARENCE ROSSER ; HANUDEL CHRISTOPHER DOUGLAS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7529962B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2009</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>MILTON DAVID WILLS</creatorcontrib><creatorcontrib>KUEMERLE MARK WILLIAM</creatorcontrib><creatorcontrib>BERHANU MALEDE WONDMAGEGNE</creatorcontrib><creatorcontrib>SMITH JACK ROBERT</creatorcontrib><creatorcontrib>OGILVIE CLARENCE ROSSER</creatorcontrib><creatorcontrib>HANUDEL CHRISTOPHER DOUGLAS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MILTON DAVID WILLS</au><au>KUEMERLE MARK WILLIAM</au><au>BERHANU MALEDE WONDMAGEGNE</au><au>SMITH JACK ROBERT</au><au>OGILVIE CLARENCE ROSSER</au><au>HANUDEL CHRISTOPHER DOUGLAS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>System for expanding a window of valid data</title><date>2009-05-05</date><risdate>2009</risdate><abstract>In one general embodiment, a design structure is provided including a first delay line having at least one buffer, the first delay line being for shifting a clock, a second delay line having at least one buffer, the second delay line being for shifting data, and a logic block adapted to identify a predetermined section of a data window. Additionally, the logic block monitors a clock signal along predetermined portions of the delay line to identify the predetermined section of the data window. Once the predetermined section of the data window is identified the logic block forwards the data associated with the predetermined section to an output pin, with the proviso that no memory element is present, and with the proviso that no feedback line is present.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | System for expanding a window of valid data |
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