Data processing system with prefetching means

The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not t...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: POL EVERT-JAN DANIEL, VAN EIJNDHOVEN JOSEPHUS THEODORUS JOHANNES, RUTTEN MARTIJN JOHAN
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator POL EVERT-JAN DANIEL
VAN EIJNDHOVEN JOSEPHUS THEODORUS JOHANNES
RUTTEN MARTIJN JOHAN
description The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks (210), wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for prefetching data into said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200). Said cache controller (300) comprises determining means (350) for identifying at least one location in said cache memory (200) containing first data, which is predicted to be dismissible without penalty and prefetch means (320) for issuing a prefetch operation replacing said first data at said location with second data, which fit said location.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US7526613B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US7526613B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US7526613B23</originalsourceid><addsrcrecordid>eNrjZNB1SSxJVCgoyk9OLS7OzEtXKK4sLknNVSjPLMkACqempZYkZ4DEc1MT84p5GFjTEnOKU3mhNDeDgptriLOHbmpBfnxqcUFicmpeakl8aLC5qZGZmaGxk5ExEUoAmI4qPQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Data processing system with prefetching means</title><source>esp@cenet</source><creator>POL EVERT-JAN DANIEL ; VAN EIJNDHOVEN JOSEPHUS THEODORUS JOHANNES ; RUTTEN MARTIJN JOHAN</creator><creatorcontrib>POL EVERT-JAN DANIEL ; VAN EIJNDHOVEN JOSEPHUS THEODORUS JOHANNES ; RUTTEN MARTIJN JOHAN</creatorcontrib><description>The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks (210), wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for prefetching data into said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200). Said cache controller (300) comprises determining means (350) for identifying at least one location in said cache memory (200) containing first data, which is predicted to be dismissible without penalty and prefetch means (320) for issuing a prefetch operation replacing said first data at said location with second data, which fit said location.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2009</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20090428&amp;DB=EPODOC&amp;CC=US&amp;NR=7526613B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20090428&amp;DB=EPODOC&amp;CC=US&amp;NR=7526613B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>POL EVERT-JAN DANIEL</creatorcontrib><creatorcontrib>VAN EIJNDHOVEN JOSEPHUS THEODORUS JOHANNES</creatorcontrib><creatorcontrib>RUTTEN MARTIJN JOHAN</creatorcontrib><title>Data processing system with prefetching means</title><description>The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks (210), wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for prefetching data into said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200). Said cache controller (300) comprises determining means (350) for identifying at least one location in said cache memory (200) containing first data, which is predicted to be dismissible without penalty and prefetch means (320) for issuing a prefetch operation replacing said first data at said location with second data, which fit said location.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNB1SSxJVCgoyk9OLS7OzEtXKK4sLknNVSjPLMkACqempZYkZ4DEc1MT84p5GFjTEnOKU3mhNDeDgptriLOHbmpBfnxqcUFicmpeakl8aLC5qZGZmaGxk5ExEUoAmI4qPQ</recordid><startdate>20090428</startdate><enddate>20090428</enddate><creator>POL EVERT-JAN DANIEL</creator><creator>VAN EIJNDHOVEN JOSEPHUS THEODORUS JOHANNES</creator><creator>RUTTEN MARTIJN JOHAN</creator><scope>EVB</scope></search><sort><creationdate>20090428</creationdate><title>Data processing system with prefetching means</title><author>POL EVERT-JAN DANIEL ; VAN EIJNDHOVEN JOSEPHUS THEODORUS JOHANNES ; RUTTEN MARTIJN JOHAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7526613B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2009</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>POL EVERT-JAN DANIEL</creatorcontrib><creatorcontrib>VAN EIJNDHOVEN JOSEPHUS THEODORUS JOHANNES</creatorcontrib><creatorcontrib>RUTTEN MARTIJN JOHAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>POL EVERT-JAN DANIEL</au><au>VAN EIJNDHOVEN JOSEPHUS THEODORUS JOHANNES</au><au>RUTTEN MARTIJN JOHAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Data processing system with prefetching means</title><date>2009-04-28</date><risdate>2009</risdate><abstract>The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks (210), wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for prefetching data into said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200). Said cache controller (300) comprises determining means (350) for identifying at least one location in said cache memory (200) containing first data, which is predicted to be dismissible without penalty and prefetch means (320) for issuing a prefetch operation replacing said first data at said location with second data, which fit said location.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US7526613B2
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Data processing system with prefetching means
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-22T12%3A31%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=POL%20EVERT-JAN%20DANIEL&rft.date=2009-04-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS7526613B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true