Package substrate and semiconductor package using the same
A package substrate may have an improved surface structure for controlling the flow of an adhesive. The package substrate may have an upper surface and a lower surface covered with a passivation layer. A window may be provided in, for example, the center of the package substrate. Sinks may be provid...
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creator | RYU JUNG-SEOK KIM PYOUNG-WAN |
description | A package substrate may have an improved surface structure for controlling the flow of an adhesive. The package substrate may have an upper surface and a lower surface covered with a passivation layer. A window may be provided in, for example, the center of the package substrate. Sinks may be provided on the lower surface, clear of the passivation layer. The semiconductor package may have an indented or non-planar surface structure. |
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The package substrate may have an upper surface and a lower surface covered with a passivation layer. A window may be provided in, for example, the center of the package substrate. Sinks may be provided on the lower surface, clear of the passivation layer. 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The package substrate may have an upper surface and a lower surface covered with a passivation layer. A window may be provided in, for example, the center of the package substrate. Sinks may be provided on the lower surface, clear of the passivation layer. The semiconductor package may have an indented or non-planar surface structure.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAKSEzOTkxPVSguTSouKUosSVVIzEtRKE7NzUzOz0spTS7JL1IogKopLc7MS1coyQCqTsxN5WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcVATal5qSXxocHmJpYWZuaWTkbGRCgBADBbLws</recordid><startdate>20090303</startdate><enddate>20090303</enddate><creator>RYU JUNG-SEOK</creator><creator>KIM PYOUNG-WAN</creator><scope>EVB</scope></search><sort><creationdate>20090303</creationdate><title>Package substrate and semiconductor package using the same</title><author>RYU JUNG-SEOK ; KIM PYOUNG-WAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7498679B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2009</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>RYU JUNG-SEOK</creatorcontrib><creatorcontrib>KIM PYOUNG-WAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RYU JUNG-SEOK</au><au>KIM PYOUNG-WAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Package substrate and semiconductor package using the same</title><date>2009-03-03</date><risdate>2009</risdate><abstract>A package substrate may have an improved surface structure for controlling the flow of an adhesive. The package substrate may have an upper surface and a lower surface covered with a passivation layer. A window may be provided in, for example, the center of the package substrate. Sinks may be provided on the lower surface, clear of the passivation layer. The semiconductor package may have an indented or non-planar surface structure.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Package substrate and semiconductor package using the same |
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