Debugging system for gate level IC designs

A synthesizer or emulator processes a gate level IC design derived from an RTL design to produce a gate level dump file indicating how signals of the gate level design behave. The gate level dump file is converted into an RTL dump file indicating how signals of the RTL design behave. A debugger proc...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	TSAI FURSHING, HSU YUIN, JONG WORI-TZY
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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