Reducing the fetch time of target instructions of a predicted taken branch instruction
A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a "branch target buffer", may store an address of a branch instruction predicted taken and the instructions beginning at the targ...
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| creator | OLSSON BRETT DOING RICHARD WILLIAM TSUCHIYA KENICHI |
| description | A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a "branch target buffer", may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced. |
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Each entry in a buffer, referred to herein as a "branch target buffer", may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20081014&DB=EPODOC&CC=US&NR=7437543B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20081014&DB=EPODOC&CC=US&NR=7437543B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OLSSON BRETT</creatorcontrib><creatorcontrib>DOING RICHARD WILLIAM</creatorcontrib><creatorcontrib>TSUCHIYA KENICHI</creatorcontrib><title>Reducing the fetch time of target instructions of a predicted taken branch instruction</title><description>A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a "branch target buffer", may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyzsOwjAQhGE3FAi4w14gDQ5KD0pEzauNjD1OLGBt2Zv7EyQKSqqRfn2zVLcT3GQDDyQjyEPsSBJeoOhJTB4gFLhInqyEyOWTDaUMF6zAzeQBpns2PP9-4FotvHkWbL67UtS1l8OxQoo9SjIWDOmv56bWza7W-63-g7wBrXU5eg</recordid><startdate>20081014</startdate><enddate>20081014</enddate><creator>OLSSON BRETT</creator><creator>DOING RICHARD WILLIAM</creator><creator>TSUCHIYA KENICHI</creator><scope>EVB</scope></search><sort><creationdate>20081014</creationdate><title>Reducing the fetch time of target instructions of a predicted taken branch instruction</title><author>OLSSON BRETT ; DOING RICHARD WILLIAM ; TSUCHIYA KENICHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US7437543B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>OLSSON BRETT</creatorcontrib><creatorcontrib>DOING RICHARD WILLIAM</creatorcontrib><creatorcontrib>TSUCHIYA KENICHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OLSSON BRETT</au><au>DOING RICHARD WILLIAM</au><au>TSUCHIYA KENICHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Reducing the fetch time of target instructions of a predicted taken branch instruction</title><date>2008-10-14</date><risdate>2008</risdate><abstract>A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a "branch target buffer", may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Reducing the fetch time of target instructions of a predicted taken branch instruction |
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